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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT181 4-bit arithmetic logic unit
Product specification Supersedes data of September 1993 File under Integrated Circuits, IC06 1998 Jun 10
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
FEATURES * Full carry look-ahead for high-speed arithmetic operation on long words * Provides 16 arithmetic operations: add, subtract, compare, double, plus 12 others * Provides all 16 logic operations of two variables: EXCLUSIVE-OR, compare, AND, NAND, NOR, OR plus 10 other logic operations * Output capability: * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT181 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT181 are 4-bit high-speed parallel Arithmetic Logic Units (ALU). Controlled by the four function select inputs (S0 to S3) and the mode control input (M), they can perform all the 16 possible logic operations or 16 different arithmetic operations on active HIGH or active LOW operands (see function table). When the mode control input (M) is HIGH, all internal carries are inhibited and the device3 performs logic operations on the individual bits as listed. When M is LOW, the carries are enabled and the "181" performs arithmetic operations on the two 4-bit words. The "181" incorporates full internal carry look-ahead and provides for either ripple carry between devices using the Cn+4 output, or for carry look-ahead between packages using the carry propagation (P) and carry generate (G) signals. P and G are not affected by carry in. ORDERING INFORMATION TYPE NUMBER 74HC181N3; 74HCT181N3 74HC181N; 74HCT181N 74HC181D; 74HCT181D PACKAGE NAME DIP24 DIP24 SO24 DESCRIPTION plastic dual in-line package; 24 leads (300 mil) plastic dual in-line package; 24 leads (600 mil) plastic small outline package; 24 leads; body width 7.5 mm standard, A=B open drain
74HC/HCT181
When speed requirements are not stringent, it can be used in a simple ripple carry mode by connecting the carry output (Cn+4) signal to the carry input (Cn) of the next unit. For high-speed operation the device is used in conjunction with the "182" carry look-ahead circuit. One carry look-ahead package is required for each group of four "181" devices. Carry look-ahead can be provided at various levels and offers high-speed capability over extremely long word lengths. The comparator output (A=B) of the device goes HIGH when all four function outputs (F0 to F3) are HIGH and can be used to indicate logic equivalence over 4 bits when the unit is in the subtract mode. A=B is an open collector output and can be wired-AND with other A=B outputs to give a comparison for more than 4 bits. The open drain output A=B should be used with an external pull-up resistor in order to establish a logic HIGH level. The A=B signal can also be used with the Cn+4 signal to indicate A > B and A < B. The function table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition (1s complement), a carry out means borrow; thus, a carry is generated when there is no under-flow and no carry is generated when there is underflow. As indicated, the "181" can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are performed to the operands.
VERSION SOT222-1 SOT101-1 SOT137-1
1998 Jun 10
2
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns
74HC/HCT181
TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay An or Bn to A=B Cn to Cn+4 CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V input capacitance power dissipation capacitance per L package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 28 17 3.5 90 30 21 3.5 92 ns ns pF pF HCT UNIT
A
B
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jun 10
3
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
PIN DESCRIPTION PIN NO. 1, 22, 20, 18 2, 23, 21, 19 6, 5, 4, 3 7 8 9, 10, 11, 13 12 14 15 16 17 24 SYMBOL B0 to B3 A0 to A3 S0 to S3 Cn M F0 to F3 GND A=B P Cn+4 G VCC NAME AND FUNCTION operand inputs (active LOW) operand inputs (active LOW) select inputs carry input mode control input function outputs (active LOW) ground (0 V) comparator output carry propagate output (active LOW) carry output carry generate output (active LOW) positive supply voltage
74HC/HCT181
ok, halfpage
2 23 21 19 1 22 20 18 7 6 5 4 3 8
A0 A1 A2 A3 B0 B1 B2 B3 Cn S0 S1 S2 S3 M
F0 9 F1 10 F2 11 F3 13 Cn+4 16 A=B G P 14 17 15
MBK219
Fig.4 Functional diagram.
Fig.5 Active HIGH operands - active LOW operands.
1998 Jun 10
4
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
FUNCTION TABLES MODE SELECT INPUTS S3 L L L L L L L L H H H H H H H H S2 L L L L H H H H L L L L H H H H S1 L L H H L L H H L L H H L L H H S0 L H L H L H L H L H L H L H L H ACTIVE HIGH INPUTS AND OUTPUTS LOGIC (M=H) A A+B AB logical 0 AB B AB AB A+B AB B AB logical 1 A+B A+B A ARITHMETIC(2) (M=L; Cn=H) A A+B A+B minus 1 A plus AB (A + B) plus AB A minus B minus 1 AB minus 1 A plus AB A plus B (A + B) plus AB AB minus 1 A plus A(1) (A + B) plus A (A + B) plus A A minus 1 MODE SELECT INPUTS S3 L L L L L L L L H H H H H H H H S2 L L L L H H H H L L L L H H H H S1 L L H H L L H H L L H H L L H H S0 L H L H L H L H L H L H L H L H
74HC/HCT181
ACTIVE LOW INPUTS AND OUTPUTS LOGIC (M=H) A AB A+B logical 1 A+B B AB A+B AB AB B A+B logical 0 AB AB A ARITHMETIC(2) (M=L; Cn=L) A minus 1 AB minus 1 AB minus 1 minus 1 A plus (A + B) AB plus (A + B) A minus B minus 1 A+B A plus (A + B) A plus B AB plus (A + B) A+B A plus A(1) AB plus A AB plus A A
Notes to the function tables 1. Each bit is shifted to the next more significant position. 2. Arithmetic operations expressed in 2s complement notation. H = HIGH voltage level L = LOW voltage level
Notes to the function tables 1. Each bit is shifted to the next more significant position. 2. Arithmetic operations expressed in 2s complement notation. H = HIGH voltage level L = LOW voltage level
1998 Jun 10
5
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
Fig.6 Logic diagram.
1998 Jun 10
6
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
Table 1 SUM MODE TEST Function inputs S0 = S3 = 4.5 V, M = S1 = S2 = 0 V PARAMETER tPLH/ tPHL tPLH/ tPHL tPLH/ tPHL tPLH/ tPHL tPLH/ tPHL tPLH/ tPHL tPLH/ tPHL tPLH/ tPHL tPLH/ tPHL INPUT UNDER TEST Ai Bi Ai Bi Ai Bi Ai Bi Cn OTHER INPUT, SAME BIT Apply 4.5 V Bi Ai Bi Ai none none none none none Apply GND none none none none Bi Ai Bi Ai none OTHER DATA INPUTS Apply 4.5 V remaining A and B remaining A and B none none remaining B remaining B remaining B remaining B all A Cn Cn
74HC/HCT181
Apply GND Fi Fi P P G G
OUTPUT UNDER TEST
remaining A and B, Cn remaining A and B, Cn remaining A, Cn remaining A, Cn remaining A, Cn remaining A, Cn all B
Cn+4 Cn+4 any F or Cn+4
Table 2 DIFFERENTIAL MODE TEST Function inputs S1 = S2 = 4.5 V, M = S0 = S3 = 0 V PARAMETER tPLH/ tPHL tPLH/ tPHL tPLH/ tPHL tPLH/ tPHL tPLH/ tPHL tPLH/ tPHL tPLZ/ tPZL tPLZ/ tPZL tPLH/ tPHL tPLH/ tPHL tPLH/ tPHL INPUT UNDER TEST Ai Bi Ai Bi Ai Bi Ai Bi Ai Bi Cn OTHER INPUT, SAME BIT Apply 4.5 V none Ai none Ai Bi none none Ai Bi none none Apply GND Bi none Bi none none Ai Bi none none Ai none OTHER DATA INPUTS Apply 4.5 V remaining A remaining A none none none none remaining A remaining A none none all A and B Apply GND remaining B, Cn remaining B, Cn remaining A and B, Cn remaining A and B, Cn remaining A and B, Cn remaining A and B, Cn remaining B, Cn remaining B, Cn remaining A and B, Cn remaining A and B, Cn none Fi Fi P P G G A=B A=B Cn+4 Cn+4 any F or Cn+4 OUTPUT UNDER TEST
Table 3 LOGIC MODE TEST Function inputs M = S1 = S2 = 4.5 V, S0 = S3 = 0 V PARAMETER tPLH/ tPHL tPLH/ tPHL INPUT UNDER TEST Ai Bi OTHER INPUT, SAME BIT Apply 4.5 V Bi Ai Apply GND none none OTHER DATA INPUTS Apply 4.5 V none none Apply GND remaining A and B, Cn remaining A and B, Cn Fi Fi OUTPUT UNDER TEST
1998 Jun 10
7
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
RATINGS (for A=B output only) Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltage are referenced to GND (ground = 0 V) SYMBOL VO -IOK -IO PARAMETER DC output voltage DC output diode current DC output source or sink current MIN. -0.5 20 25 MAX. +7.0 V mA mA UNIT
74HC/HCT181
CONDITIONS for VO < -0.5 V for -0.5 V < VO
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HC SYMBOL PARAMETER +25
min. typ. max.
TEST CONDITIONS UNIT VCC (V) 2.0 to 6.0 VIL OTHER
-40 to +85
min. max.
-40 to +125
min. max.
IOZ
HIGH level output leakage current
0.5
5.0
10.0
A
VIL
note 1 VO = 0 or 6 V
Note to the DC characteristics 1. The maximum operating output voltage (VO(max)) is 6.0 V.
1998 Jun 10
8
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25
min. typ.
74HC/HCT181
TEST CONDITIONS UNIT V MODE OTHER CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 M = 0 V; Fig.9; Tables 1 and 2 M = 0 V; Fig.9; Tables 1 and 2 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2
-40 to +85 -40 to +125
max. min. max. min. max.
tPHL/ tPLH
propagation delay Cn to Cn+4 propagation delay Cn to Fn propagation delay An to G propagation delay Bn to G propagation delay An to G propagation delay Bn to G propagation delay An to P propagation delay Bn to P propagation delay An to P propagation delay Bn to P propagation delay Ai to Fi propagation delay Bi to Fi propagation delay Ai to Fi propagation delay Bi to Fi
55 20 16 69 25 20 72 26 21 77 28 22 76 26 21 77 28 22 61 22 18 63 23 18 55 20 16 63 23 18 77 28 22 85 31 25 77 28 22 83 31 24
165 33 28 200 40 34 210 42 36 230 46 39 215 43 37 240 48 41 185 37 31 195 39 33 170 34 29 195 39 33 230 46 39 255 51 43 235 47 40 255 51 43
205 41 35 250 50 43 265 53 45 290 58 49 270 54 46 300 60 51 230 46 39 245 49 42 215 43 37 245 49 42 290 58 49 320 64 54 295 59 50 320 64 54 9
250 50 43 300 60 51 315 63 54 345 69 59 320 65 55 360 72 61 280 56 48 295 59 50 255 51 43 295 59 50 345 69 59 385 77 65 355 71 60 385 77 65
sum diff sum diff sum
tPHL/ tPLH
ns
tPHL/ tPLH
ns
tPHL/ tPLH
ns
sum
tPHL/ tPLH
ns
diff
tPHL/ tPLH
ns
diff
tPHL/ tPLH
ns
sum
tPHL/ tPLH
ns
sum
tPHL/ tPLH
ns
diff
tPHL/ tPLH
ns
diff
tPHL/ tPLH
ns
sum
tPHL/ tPLH
ns
sum
tPHL/ tPLH
ns
diff
tPHL/ tPLH
ns
diff
1998 Jun 10
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
Tamb (C) 74HC SYMBOL PARAMETER +25
min. typ.
TEST CONDITIONS
MODE OTHER UNIT V CC (V)
-40 to +85 -40 to +125
max. min. max. min. max.
tPHL/ tPLH
propagation delay Ai to Fi propagation delay Bi to Fi propagation delay An to Cn+4 propagation delay Bn to Cn+4 propagation delay An to Cn+4 propagation delay Bn to Cn+4 propagation delay An to A=B propagation delay Bn to A=B propagation delay An to Fn propagation delay Bn to Fn propagation delay An to Fn propagation delay Bn to Fn output transition time
74 27 22 83 30 24 80 29 23 80 29 23 77 28 22 85 31 25 80 29 23 88 32 26 83 30 24 85 31 25 77 28 22 88 32 26 19 7 6
230 46 39 255 51 43 235 47 40 235 47 40 235 47 40 255 51 43 245 49 42 270 54 46 255 51 43 265 53 45 240 48 41 275 55 47 75 15 13
290 58 49 320 64 54 295 59 50 295 59 50 295 59 50 320 64 54 305 61 52 340 68 58 320 64 54 330 66 56 300 60 51 345 69 59 95 19 16
345 69 59 385 77 65 355 71 60 355 71 60 355 71 60 385 77 65 370 74 63 405 81 69 385 77 65 400 80 68 360 72 61 415 83 71 110 22 19
ns
2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0
logic
M = 4.5 V; Fig.8; Table 3 M = 4.5 V; Fig.8; Table 3 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.8; Table 1 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.8; Table 1 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.10; Table 2 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.10; Table 2 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.11; Table 2 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.11; Table 2 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 note ; Figs 7 and 11
tPHL/ tPLH
ns
logic
tPHL/ tPLH
ns
sum
tPHL/ tPLH
ns
sum
tPHL/ tPLH
ns
diff
tPHL/ tPLH
ns
diff
tPZL/ tPLZ
ns
diff
tPZL/ tPLZ
ns
diff
tPHL/ tPLH
ns
sum
tPHL/ tPLH
ns
sum
tPHL/ tPLH
ns
diff
tPHL/ tPLH
ns
diff
tTHL/ tTLH
ns
Note to the AC characteristics 1. For the open drain output (A=B) only tTHL is valid.
1998 Jun 10
10
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HCT SYMBOL PARAMETER +25
min. typ. max.
74HC/HCT181
TEST CONDITIONS UNIT VCC (V) 2.0 to 6.0 VIL OTHER
-40 to +85
min. max.
-40 to +125
min. max.
IOZ
HIGH level output leakage current
0.5
5.0
10.0
A
VIL
note 1 VO = 0 or 6 V
Note to the DC characteristics 1. The maximum operating output voltage (VO(max)) is 6.0 V. Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT Cn, M An, Bn Sn
UNIT LOAD COEFFICIENT 0.50 0.75 1.00
1998 Jun 10
11
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85
max.
74HC/HCT181
TEST CONDITIONS UNIT V MODE OTHER CC (V) ns 4.5 sum diff sum diff sum M = 0 V; Fig.9; Tables 1 and 2 M = 0 V; Fig.9; Tables 1 and 2 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1
-40 to +125
min. max.
min. typ. max. min.
tPHL/ tPLH
propagation delay Cn to Cn+4 propagation delay Cn to Fn propagation delay An to G propagation delay Bn to G propagation delay An to G propagation delay Bn to G propagation delay An to P propagation delay Bn to P propagation delay An to P propagation delay Bn to P propagation delay Ai to Fi propagation delay Bi to Fi
25
42
53
63
tPHL/ tPLH
28
48
60
72
ns
4.5
tPHL/ tPLH
31
54
68
81
ns
4.5
tPHL/ tPLH
32
54
68
81
ns
4.5
sum
tPHL/ tPLH
31
54
68
81
ns
4.5
diff
tPHL/ tPLH
31
54
68
81
ns
4.5
diff
tPHL/ tPLH
23
41
51
62
ns
4.5
sum
tPHL/ tPLH
24
41
51
62
ns
4.5
sum
tPHL/ tPLH
23
40
50
60
ns
4.5
diff
tPHL/ tPLH
23
40
50
60
ns
4.5
diff
tPHL/ tPLH
33
58
73
87
ns
4.5
sum
tPHL/ tPLH
34
58
73
87
ns
4.5
sum
1998 Jun 10
12
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85
max.
TEST CONDITIONS MODE OTHER UNIT V CC (V) ns 4.5 diff M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 M = 4.5 V; Fig.8; Table 3 M = 4.5 V; Fig.8; Table 3 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.8; Table 1 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.8; Table 1 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.10; Table 2 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.10; Table 2 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.11; Table 2 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.11; Table 2 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1 M = S1 = S2 = 0 V; S0 = S3 = 4.5 V; Fig.7; Table 1
-40 to +125
min. max.
min. typ. max. min.
tPHL/ tPLH
propagation delay Ai to Fi propagation delay Bi to Fi propagation delay Ai to Fi propagation delay Bi to Fi propagation delay An to Cn+4 propagation delay Bn to Cn+4 propagation delay An to Cn+4 propagation delay Bn to Cn+4 propagation delay An to A=B propagation delay Bn to A=B propagation delay An to Fn propagation delay Bn to Fn
33
57
71
86
tPHL/ tPLH
33
57
71
86
ns
4.5
diff
tPHL/ tPLH
29
54
68
81
ns
4.5
logic
tPHL/ tPLH
33
54
68
81
ns
4.5
logic
tPHL/ tPLH
30
53
66
80
ns
4.5
sum
tPHL/ tPLH
31
53
66
80
ns
4.5
sum
tPHL/ tPLH
30
55
69
83
ns
4.5
diff
tPHL/ tPLH
34
55
69
83
ns
4.5
diff
tPZL/ tPLZ
34
60
75
90
ns
4.5
diff
tPZL/ tPLZ
35
60
75
90
ns
4.5
diff
tPHL/ tPLH
33
56
70
84
ns
4.5
sum
tPHL/ tPLH
33
56
70
84
ns
4.5
sum
1998 Jun 10
13
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85
max.
TEST CONDITIONS MODE OTHER UNIT V CC (V) ns 4.5 diff M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 M = S0 = S3 = 0 V; S1 = S2 = 4.5 V; Fig.8; Table 2 Figs 7 and 11; note 1
-40 to +125
min. max.
min. typ. max. min.
tPHL/ tPLH
propagation delay An to Fn propagation delay An to Fn output transition time
32
56
70
84
tPHL/ tPLH
33
56
70
84
ns
4.5
diff
tTHL/ tTLH
7
15
19
22
ns
4.5
Note to the AC characteristics 1. For the open drain output (A=B) only tTHL is valid.
1998 Jun 10
14
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
AC WAVEFORMS
74HC/HCT181
Fig.7
Propagation delays for carry input to carry output, carry input to function outputs, operands to carry generate operands, propagation outputs and output transition lines.
Fig.8
Propagation delays for operands to carry generate, propagate outputs and function outputs.
Fig.9
Propagation delays for operands to carry output and function outputs.
Fig.10 Propagation delays for operands to carry output. Note to AC waveforms
(1)
HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
APPLICATION INFORMATION
Fig.11 Waveforms showing the input (Ai, Bj) to output (A=B) propagation delays and output transition time of the open drain output (A=B).
A and B inputs and F outputs of "181" are not shown
Fig.12 Application example showing 16-bit ALU ripple-carry configuration. 15
1998 Jun 10
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
PACKAGE OUTLINES DIP24: plastic dual in-line package; 24 leads (300 mil)
74HC/HCT181
SOT222-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 24 13 wM (e 1) MH
pin 1 index E
1
12
0
5 scale
10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT mm inches A max. 4.70 0.185 A1 min. 0.38 0.015 A2 max. 3.94 0.155 b 1.63 1.14 0.064 0.045 b1 0.56 0.43 0.022 0.017 c 0.36 0.25 0.014 0.010 D (1) 31.9 31.5 1.256 1.240 E (1) 6.73 6.48 0.265 0.255 e 2.54 0.100 e1 7.62 0.300 L 3.51 3.05 0.138 0.120 ME 8.13 7.62 0.32 0.30 MH 10.03 7.62 0.395 0.300 w 0.25 0.01 Z (1) max. 2.05 0.081
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT222-1 REFERENCES IEC JEDEC MS-001AF EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-03-11
1998 Jun 10
16
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
DIP24: plastic dual in-line package; 24 leads (600 mil)
SOT101-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 24 13 MH wM (e 1)
pin 1 index E
1
12
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 5.1 0.20 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.7 1.3 0.066 0.051 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 32.0 31.4 1.26 1.24 E (1) 14.1 13.7 0.56 0.54 e 2.54 0.10 e1 15.24 0.60 L 3.9 3.4 0.15 0.13 ME 15.80 15.24 0.62 0.60 MH 17.15 15.90 0.68 0.63 w 0.25 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT101-1 REFERENCES IEC 051G02 JEDEC MO-015AD EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-23
1998 Jun 10
17
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013AD EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
1998 Jun 10
18
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
74HC/HCT181
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1998 Jun 10
19
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
74HC/HCT181
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1998 Jun 10
20

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